The present invention relates to a normally-off semiconductor device with low on-resistance and to a circuit analog of such device.
A junction field-effect transistor(hereinafter designated JFET) of the N-channel type typically comprises a channel region of N-type semiconductor material and a P-type gate region adjoining the N-type channel region and forming a P-N junction therewith. Upon reverse biasing of this P-N junction through appropriate biasing of the P-type gate region, a depletion region is formed in the vicinity of the P-N junction and extends into the N-type channel region so as to shrink the portion of the channel that can conduct current. When the depletion region has spread across the entire channel, the JFET is in, what is known in the art as, a pinched-off condition in which it cannot conduct current.
A JFET is a normally-on device; that is, a JFET's gate region must be biased in order to pinch off the JFET. In many applications, however, it is desirable to have normally-off device operation. Such normally-off operation is achieved in an electrical circuit described and claimed in the above-referenced application. In such circuit, a JFET is serially connected to a bipolar transistor, with the base electrode of the bipolar transistor serving as a gate or control electrode for the circuit. Normally-off operation of the JFET is achieved because the base electrode must be appropriately biased to turn on the bipolar transistor and allow the JFET to conduct current.
In the foregoing electrical circuit, the gate of the JFET is electrically shorted to the emitter of the bipolar transistor, resulting in the P-N junction of the JFET being reverse-biased, at least to a slight extent, while the JFET is conducting current. As a consequence, the circuit cannot take advantage of a technique for markedly lowering the on-resistance of a JFET, which involves forward-biasing the P-N junction of the JFET. With the P-N junction sufficiently forward-biased, the P-type gate region injects holes into the N-type channel, resulting in a lowering of the channel resistance, and hence, lowering of the on-resistance of the JFET. By controlling the level of the biasing voltage on the JFET's gate, the extent of carrier injection into the N-type channel and, hence, the onresistance of the JFET, is modulated. This technique is discussed in detail in an article by B. J. Baliga, entitled "Bipolar Operation of Power Junction Gate Field-Effect-Transistors", Electron Letters, Vol. 16 (1980), pages 300-301, which is incorporated herein by reference.
It would be desirable to provide a JFET that operates in a normally-off fashion, yet which achieves a markedly reduced on-resistance through forward-biasing of its P-N junction.